1. Field of the Invention
This invention relates to MOS devices having LDD regions with graded junctions and methods of making same.
2. Description of the Related Art
In the continuing design of VLSI devices or chips with an ever increasing number of transistors and associated circuitry formed on the same amount of space, shrinkage or sizing down of each component has created further problems which must be dealt with in the construction of the VLSI chip. The shrinkage in size of MOS transistors results in a shorter channel length and this has created problems with respect to the electric field created near the drain region which can cause short channel effects or punchthrough in which the current begins to flow in uncontrolled form through the substrate beneath the channel.
To remedy this short channel or punch through effect, it has been proposed to grade the doping or impurities in the substrate by forming a lightly doped drain region (LDD) adjacent the channel with a more heavily and deeper doped drain region, in turn, formed adjacent the LDD region. The reduced or spread out fields of the lightly doped drain structure mitigates short-channel effects, reduce hot-carrier generation, and increase the junction breakdown voltage.
The problems of lower junction breakdown voltage and hot electron injection due to the sharp impurity profile of the drain junction and the proposed remedy of forming a lightly doped drain region were first discussed by Bassous et al in an article entitled "Self-Aligned Polysilicon Gate MOSFETs with Tailored Source and Drain Profiles" which appeared in IBM Technical Disclosure Bulletin Vol. 22, No. 11, in April 1980. Bassous et al proposed thermally oxidizing a polysilicon gate and the silicon substrate followed by reactive ion etching to form an oxide sidewall on the polysilicon gate following which source and drain regions in the substrate were implanted N+ using the oxide sidewall as a shield. The oxide sidewall was then stripped followed by an N- implant to form N- or lightly doped source and drain regions in the substrate between the N+ source and drain regions and the channel beneath the gate electrode.
FIGS. 1 and 2 illustrate how such lightly doped source and drain regions (LDD regions) are typically formed in this method. Oxide spacers 14 are formed on the side of a polysilicon strip 10 which forms the gate electrode, over gate oxide 16, for several MOS transistors formed in exposed portions of silicon substrate 20 under field oxide 18 as best seen in FIG. 1. Oxide spacers 14 are formed by depositing or growing a layer of oxide (silicon dioxide) over the structure including polysilicon strip 10 and then RIE etching the structure to remove the majority of the oxide leaving only the oxide spacers 14 due to their increased thickness in the step region of the oxide layer caused by the raised polysilicon strip.
The structure may then be N+ implanted to form the N+ source and drain regions 17 shown in FIG. 2 with oxide shoulders 14 shielding the substrate region immediately adjacent the channel region to be formed under gate electrode 10. Subsequently oxide shoulders 14 are removed, thereby permitting an N- implant in the previously shielded regions of the substrate shown outlined in dotted lines at 15.
Earlier, in an article entitled "A Quadruply Self-Aligned MOS (QSA MOS) A New Short Channel High Speed High Density MOSFET for VLSI" published at pp. 581-584 in IEDM in 1979, Ohta et al had proposed controlling or grading the depth of a single implant by forming a layer of oxide over a polysilicon gate electrode and then forming a nitride layer over the oxide layer which was patterned to extend laterally beyond the polysilicon gate and over a portion of the oxide layer over the substrate. The oxide layer was then reactive ion etched, using this nitride portion as a mask, resulting in horizontal portions of oxide remaining on the substrate extending laterally from the polysilicon gate electrode. A subsequent source and drain ion implant gave rise to deeper implanted regions further away from the gate electrode and more shallow implantation where the ions passed through the oxide layer resulting in shallow and deep implanted source and drain regions.
Subsequent to these publications, others have also published proposed methods of forming such lightly doped drain regions. Ogura et al, in "Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field-Effect Transistor", published in the IEEE Transactions on Electron Devices, Vol. ED-27, No. 8, in August of 1980, describe a method for forming such regions by first forming a column on a substrate comprising a polysilicon layer, a silicon nitride layer, and a silicon oxide layer. Using this column as a mask, the substrate is N+ implanted after which the polysilicon is overetched, undercutting the overlying nitride and oxide layers. The oxide and nitride layers are then removed and the substrate is then N- implanted to form N- regions in the substrate area beneath where the polysilicon was removed after the N+ implantation.
Tsang et al, in a paper entitled "Fabrication of High-Performance LDDFET's with Oxide Sidewall-Spacer Technology", published in the IEEE Transactions on Electron Devices, Vol. ED-29, No. 4, in April 1982, describe a method of forming LDD regions by first forming a polysilicon gate electrode, N- doping the substrate around the gate electrode, forming a silicon oxide layer over the structure which is then RIE etched to form oxide spacers on the sidewalls of the polysilicon gate electrode. Using these spacers as shields, the substrate is then N+ implanted. The original N- doping results in the formation of LDD regions between the channel under the gate electrode and the N+ regions source and drain subsequently implanted in the substrate.
Woo et al U.S. Pat. No. 4,728,617 discloses a method of fabricating a MOSFET with graded source and drain regions by growing a thermal oxide layer over a substrate on which has already been formed a gate electrode over gate oxide. A low temperature oxide is then deposited over the thermal oxide layer and the structure is then RIE etched to remove substantially all of the low temperature oxide except for spacers on the side of the raised thermal oxide layer adjacent the sides of the gate electrode. In one embodiment the structure is then implanted with a dopant which penetrates through the thermal oxide layer into the substrate except where the thermal oxide is shielded by the low temperature oxide spacers. The spacers are then removed, as well as the thermal oxide not previously shielded by the low temperature oxide, leaving only the thermal oxide portions previously below the spacers. The structure is then implanted a second time wherein the thermal oxide previously below the spacers acts to partially shield the substrate resulting in a shallow implant adjacent the channel portion below the gate electrode. In a second embodiment, the spacers are removed prior to any implantation and most of the thermal oxide layer not beneath the spacers is also removed, leaving only a thick thermal oxide, which may comprise either a single thickness or two thicknesses. The structure is then implanted with a dopant in a single implantation step wherein the remaining thermal oxide portions partially shield the substrate adjacent the channel region beneath the gate electrode resulting in a shallower implant beneath the thermal oxide portions.
Parillo et al, in an article entitled "A Versatile, High-Performance, Double-Level-Poly Double-Level-Metal, 1.2-Micron CMOS Technology", IDEM, 1986, pp. 244-247, describe constructing MOS devices using a disposable polysilicon spacer which is formed on the sidewall of the gate electrode following which an N+ implant to form source and drain regions is performed. The polysilicon spacers are then removed and an N- implant is made resulting in N- regions in the substrate adjacent to the gate electrode and separating the N+ regions from the channel formed in the substrate beneath the gate electrode.
Although many ways have thus been proposed to solve the short channel and punchthrough problem, including many ways of forming the lightly doped drain region, the use of oxide spacers has been the most widely used approach. However while the RIE etching of the oxide layer may use the underlying silicon 20 as an etch stop or end point for the etch, as shown in FIG. 2, in the field oxide region between adjacent MOS devices, there may be no silicon at the surface of the structure and the RIE etching will etch away grooves in the field oxide which, if not filled, can adversely affect the topography, and, if filled, can result in the formation of voids in the filler material which can subsequently result in reliability problems from inclusion of contaminants. Also if the voids are exposed, they may etch preferentially or oxidize which can, in turn, stress the substrate.
To avoid the problem of over etching into the field oxide between adjacent devices, it has been proposed, as discussed above, for example, with regard to the Parillo et al article, to replace the prior art oxide spacers or shoulders shown in FIGS. 1 and 2 with polysilicon spacers which would be formed by RIE etching a conformal polysilicon layer which would be formed over the structure (after first forming a thin oxide layer which would serve to separate the polysilicon gate strip from the conformal polysilicon layer). However, the use of a conductive material such as polysilicon to form the spacers adjacent the gate electrode necessitates the subsequent removal of such polysilicon spacers since they would be electrically floating and could cause threshold shifts.
Thus, there remained a need for solving the problem of short channel effects such as punchthrough in MOS transistors used in VLSI structures by constructing lightly doped drain regions without incurring the additional problems of the prior art which occurred when either oxide or polysilicon spacers were used in the course of the formation of such lightly doped source and drain regions.
European Patent Application 0,218,408 describes a process for forming LDD structures in integrated circuits. Three layers are formed over a gate electrode on a substrate. The bottom layer is an oxide layer; the middle layer is a nitride layer; and the top layer is a polysilicon layer. The polysilicon layer is then etched with an anisotropic dry etch to remove the polysilicon layer except for spacers left along the sides of the raised gate electrode. The substrate is then implanted with a heavy concentration of dopant, using the polysilicon spacers as a shield. After the first implantation, the polysilicon spacers are removed and the substrate is again implanted to form less heavily doped regions in the substrate in the areas previously shielded by the polysilicon spacers and adjoining the heavily doped regions of the substrate.
Komori et al Japanese Patent Document 60-241,267 describes a process to prevent damage to a substrate wherein a polysilicon sidewall is formed without completely etching a surface oxide film in a MOSFET of off-set structure. A gate oxide is first formed on a substrate followed by formation of a gate electrode over the gate oxide. A silicon oxide film is then formed over the entire structure and a nitride film is formed over the oxide layer. A polysilicon film is then formed which is RIE etched to form sidewalls or spacers on the side of the gate electrode (over the nitride and oxide layers). The nitride film acts an an etch stop during the etching of the polysilicon layer resulting in no removal of the underlying silicon oxide layer which, in turn, prevents damage to the substrate.
However, these teachings still utilize the spacers as the mask for shielding the structure when implanting to form the conventional source and drain regions in the substrate.
In copending U.S. patent application Ser. No. 127,995, filed Dec. 2, 1987, by Jacob Haskell and assigned to the assignee of this invention, entitled "METHOD OF MAKING A HIGH PERFORMANCE MOS DEVICE HAVING LDD REGIONS WITH GRADED JUNCTIONS", cross-reference to which is hereby made, there is described and claimed a method of making such LDD source and drain regions in MOS devices which comprises: forming over one or more gate electrodes on a substrate a shielding layer of an insulating material such as silicon nitride; forming another layer of a dissimilar material over the shielding layer such as an oxide or polysilicon layer; anisotropically etching the layer of dissimilar material over the shielding layer to remove the layer except for spacer portions over the shielding layer adjacent the sidewalls of the gate electrodes; removing the portions of the shielding layer not masked by the spacer portions, resulting in the formation of one or more el-shaped shielding members each having a vertical portion against the gate electrode and a horizontal leg extending over the substrate from the vertical portion; and then removing the spacer portions over the one or more el-shaped shielding members.
These el-shaped shielding members then serve as masks to permit the respective formation of conventional P+ or N+ doped source and drain regions in the substrate portion not masked by the el-shaped shielding members using a low energy, but high concentration, implantation which will not penetrate through the el-shaped shielding members. The substrate is also implanted with a low concentration of dopant material of the same type, but at an energy level sufficiently high to penetrate through the el-shaped shielding member to form lightly doped source/drain regions in the portions of the substrate beneath, i.e., shielded, by the el-shaped shielding members. This results in the formation of lightly doped source and drain regions, e.g., P- or N- LDD regions, in the substrate between the channel region of the substrate beneath the gate electrode and the conventional P+ or N+ source and drain regions formed in the substrate.
In one embodiment described therein, when one or more MOS devices of a first type are formed, the remaining portion of the substrate is masked with a first photoresist mask. Following formation of the MOS devices of the first type, the photoresist mask is removed and the MOS devices just formed are masked with a second photoresist mask while one or more MOS devices of a second (opposite) conductivity type are formed.
In a second embodiment described in the aforementioned Haskell patent application, after formation of the spacer members over the shielding layer, the first mask is applied, before removal of the portions of the underlying shielding layer not masked by the spacers. The portions of the shielding layer not covered by either the spacers or the photoresist mask are then removed followed by removal of the first photoresist mask. The remainder of the shielding layer, the el-shaped members, then act as a mask during formation of the MOS devices of the first type. However, while this second embodiment does eliminate the presence of the first photoresist mask during the implantation steps to form the MOS devices of the first type, the method still requires the use of two photoresist masks. Since each photoresist mask used may result in processing problems which negatively impact on the yield of chips from a wafer, it would be desirable from a standpoint of process economics, to completely eliminate the formation and use of one of the photoresist masks.